Since film formation conditions for devices employing organic semiconductors are milder than those for conventional inorganic semiconductor devices, it is possible to form semiconductor thin films on various substrates and to perform film formation at room temperature, whereby cost reduction, and flexibility of thin films due to the formation thereof on polymer films have been anticipated.
As organic semiconductor materials, conjugated polymers and oligomers such as polyphenylvinylene, polypyrrole, polythiophene, or oligothiophene, as well as polyacene compounds such as anthracene, tetracene, or pentacene have been investigated.
It is reported that specifically, since a polyacene compound exhibits high crystallinity due to its strong intermolecular cohesive force, high carrier mobility and therefore excellent semiconductor device properties are exhibited, which is described, for example, in Shon et al., Science, Vol. 289, p. 559 (2000); Shon et al., Nature, Vol. 403, p. 408 (2000); and Cloke et al., IEEE Transactions on Electron Devices, Vol. 46, p. 1258 (1999).
In contrast, since it is possible to form a thin film by coating a solution of a conjugated polymer such as a polythiophene compound, it has been anticipated to prepare elements at low cost via pattern formation employing a printing method (for example, refer to Sirringhaus et al., Science, Vol. 290, p. 2123 (2000)).
Now, as methods for forming electrodes of the organic semiconductor elements described above, there are proposed a method for forming an electrode pattern via etching or lift-off of a uniformly formed metal thin film (a first method), a method for forming an electrode pattern by printing a paint containing a metal filler (a second method), or a method for forming an electrode pattern by printing a conductive polymer solution (a third method).
However, in the first method, since it is necessary to form a resist layer for pattern formation and to remove the resist layer, there has been a continuing problem in that the pattern formation process was cumbersome. Further, in the second and the third method, a problem has been that resistance of the electrode was increased due to the effect of a binder contained.
Thus, Patent Document 1 describes that a low resistance electrode is readily formed employing electroless plating. This is a method wherein an electrode pattern is readily formed in combinations of a catalyst inducing electroless plating, a plating agent, and patterning therewith, whereby electrode pattern formation becomes possible via no cumbersome steps.
However, when an organic semiconductor layer comes in contact with a plating catalyst liquid or a plating agent, its transistor properties are likely to significantly deteriorate due to changes of the organic semiconductor layer. Further, a common electroless plating method has the problem in that pattern accuracy is too low. The present invention can improve these problems significantly.
Patent Document 1: Japanese Patent Publication Open to Public Inspection (hereinafter, referred to as JP-A) No. 2004-158805